DocumentCode :
2455524
Title :
Modeling and scaling evaluation of junction-free charge-trapping NAND flash devices
Author :
Hsiao, Yi-Hsuan ; Lue, Hang-Ting ; Hsieh, Kuang-Yeu ; Liu, Rich ; Lu, Chih-Yuan
Author_Institution :
Emerging Central Lab., Macronix Int. Co. Ltd., Hsinchu, Taiwan
fYear :
2009
fDate :
27-29 April 2009
Firstpage :
103
Lastpage :
104
Abstract :
The ldquojunction-freerdquo charge-trapping NAND flash [1,2] is studied extensively. Simulation results show that the junction-free NAND flash is scalable beyond 15 nm node (half pitch) with reasonable DC characteristics, while the conventional ldquowith-junctionrdquo NAND device shows much worse short-channel effect. Simulation results show that lower p-well doping and smaller space (S) between the WL´s are two key factors to enable the higher performance of junction-free NAND device. For the first time, we point out that the parameters of the region under the space (S) such as interface traps (Dit), parasitic trapped charge, and local p-well doping have strong impact on cell characteristics. Experimental results on junction-free BE-SONOS device showed some discrepancy with the simulation that may be due to non-ideal factors under the space. Finally, the feasibility of junction-free device on SOI for the future 3D NAND Flash is also examined.
Keywords :
NAND circuits; flash memories; interface traps; junction-free BE-SONOS device; junction-free charge-trapping NAND flash devices; p-well doping; parasitic trapped charge; scaling evaluation; short-channel effect; Doping; Electron traps; Interference; Space charge;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on
Conference_Location :
Hsinchu
ISSN :
1524-766X
Print_ISBN :
978-1-4244-2784-0
Electronic_ISBN :
1524-766X
Type :
conf
DOI :
10.1109/VTSA.2009.5159311
Filename :
5159311
Link To Document :
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