Communication mechanisms for parallel DSP systems on a chip

Author

Williams, Joseph ; Ackland, Bryan ; Heintze, Nevin

Author_Institution

Circuits & Syst. Technol. Lab., Agere Syst., Holmdel, NJ, USA

fYear

2002

fDate

2002

Firstpage

420

Lastpage

422

Abstract

We consider the implication of deep sub-micron VLSI technology on the design of communication frameworks for parallel DSP systems-on-chip. We assert that distributed data transfer and control mechanisms are necessary to manage many independent processing subsystems and software tasks. An example of a parallel DSP architecture is given and used to demonstrate these mechanisms at work. We show the similarity of these mechanism and those used in large scale computing networks

Keywords

application specific integrated circuits; digital signal processing chips; integrated circuit design; parallel architectures; programmable circuits; VLSI circuit design; communication framework design; control mechanisms; deep sub-micron VLSI technology; distributed computing; distributed data transfer; large scale computing networks; packet switched I/O subsystem; parallel DSP architecture; parallel DSP systems-on-chip; processing subsystems; routing delays; software tasks; Communication system control; Delay; Digital signal processing; Digital signal processing chips; Distributed control; Integrated circuit interconnections; Multiprocessor interconnection networks; System-on-a-chip; Transistors; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

Conference_Location

Paris

ISSN

1530-1591

Print_ISBN

0-7695-1471-5

Type

conf

DOI

10.1109/DATE.2002.998308

Filename

998308