DocumentCode
2455903
Title
A polynomial time optimal diode insertion/routing algorithm for fixing antenna problem
Author
Huang, Li-Da ; Tang, Xiaoping ; Xiang, Hua ; Wong, Derek ; Liu, I-Min
Author_Institution
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
fYear
2002
fDate
2002
Firstpage
470
Lastpage
475
Abstract
Antenna problem is a phenomenon of plasma induced gate oxide degradation. It directly affects manufacturability of VLSI circuits, especially in deep-submicron technology using high density plasma. Diode insertion is a very effective way to solve this problem Ideally diodes are inserted directly under the wires that violate antenna rules. But in today\´s high-density VLSI layouts, there is simply not enough room for "under-the-wire" diode insertion for all wires. Thus it is necessary to insert many diodes at legal "off-wire" locations and extend the antenna-rule violating wires to connect to their respective diodes. Previously only simple heuristic algorithms were available for this diode insertion and routing problem. In this paper we show that the diode insertion and routing problem for an arbitrary given number of routing layers can be optimally solved in polynomial time. Our algorithm guarantees to find a feasible diode insertion and routing solution whenever one exists. Moreover we can guarantee to find a feasible solution to minimize a cost function of the form α · L + β · N where L is the total length of extension wires and N is the total number of Was on the extension wires. Experimental results show that our algorithm is very efficient
Keywords
VLSI; integrated circuit interconnections; integrated circuit layout; integrated circuit reliability; integrated circuit yield; minimisation; plasma materials processing; sputter etching; IC yield; VLSI circuit; cost function; deep-submicron technology; diode insertion; gate oxide degradation; heuristic algorithms; high-densily VLSI layouts; manufacturability; off-wire locations; plasma effects; reliability; routing solution; Circuits; Degradation; Diodes; Manufacturing; Plasma density; Plasma materials processing; Polynomials; Routing; Very large scale integration; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location
Paris
ISSN
1530-1591
Print_ISBN
0-7695-1471-5
Type
conf
DOI
10.1109/DATE.2002.998315
Filename
998315
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