Title :
Tri-gated poly-Si nanowire SONOS devices
Author :
Hsing-Hui Hsu ; Ta-Wei Liu ; Chuan-Ding Lin ; Chiu Kuo-Jung ; Tiao-Yuan Huang ; Horng-Chih Lin
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
In this work, a simple and cost-effective approach to integrate planar poly-Si thin-film transistors (TFTs) and tri-gated poly-Si NW SONOS devices was proposed without resorting to advanced lithographic tools. Greatly enhanced P/E speed with the use of NW structure was clearly demonstrated. It was observed that the method developed in the work for integration of planar TFTs and NW SONOS devices can be easily implemented in modern flat-panel manufacturing without resorting to costly lithography. Based on the results obtained in this work, the proposed method appears to be very promising for the realization of system-on-panel (SOP).
Keywords :
nanowires; silicon; thin film transistors; Si; modern flat-panel manufacturing; planar polysilicon thin-film transistors; system-on-panel; trigated polysilicon nanowire SONOS devices; Fabrication; Laboratories; Manufacturing; Nanoscale devices; Nonvolatile memory; SONOS devices; Temperature measurement; Thin film transistors; Tunneling; Voltage;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-2784-0
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2009.5159333
