DocumentCode :
2456078
Title :
Power crisis in SoC design: strategies for constructing low-power, high-performance SoC designs
Author :
Brock, K. ; Edwards, C. ; Lannoo, R. ; Schlichtmann, U. ; Domic, A. ; Benkoski, J. ; Overhauser, D. ; Kliment, M.
Author_Institution :
Virtual Silicon, US
fYear :
2002
fDate :
4-8 March 2002
Firstpage :
538
Lastpage :
538
Abstract :
This special panel session brings together several leading technologists to discuss the challenges and solutions in constructing SoC designs that achieve their performance goals within a very tight power budget. These challenges are addressed from the often conflicting perspectives of semiconductor design teams and commercial solutions providers of EDA construction tools, EDA analysis tools and semiconductor IP (SIP).
Keywords :
Design methodology; Design optimization; Electronic design automation and methodology; Electronic equipment testing; LAN interconnection; Performance analysis; Signal design; Signal synthesis; Silicon; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location :
Paris, France
ISSN :
1530-1591
Print_ISBN :
0-7695-1471-5
Type :
conf
DOI :
10.1109/DATE.2002.998352
Filename :
998352
Link To Document :
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