Roughness characterization of gate all around Silicon Nano Wire fabrication

In this paper we present a new methodology to calibrate and correct in line roughness measurements for Silicon Nano Wires (SiNW) fabrication processes. For successful implementation of these processes in industry, the Silicon Nano Wires (SiNW) with widths of 5-25 nm should be characterized in the framework of Secondary Electron Microscope(CD SEM) Metrology. Different smoothing processes yield SiNWs with edge roughness values in the sub nanometer range[1]. Such small differences in roughness values provide an interesting opportunity to evaluate sensitivity of the SEM metrology algorithms and measurement accuracy. A simulation program modeling SEM images including small features was developed, taking into account the main factors that affect the SEM signal formation. Synthetic (simulated) images of SiNW in a range of 5-25 nm and roughness of 0-1 nm were produced. Using synthetic images with added Line Edge Roughness (LER), we characterized the performance and sensitivity of LER algorithms and CD metrics.