DocumentCode
2456194
Title
Analog circuit sizing using adaptive worst-case parameter sets
Author
Schwencker, R. ; Schenkel, F. ; Pronath, M. ; Graeb, H.
Author_Institution
Inst. for Electron. Design Autom., Tech. Univ. of Munich, Germany
fYear
2002
fDate
2002
Firstpage
581
Lastpage
585
Abstract
In this paper a method for nominal design of analog integrated circuits is presented that includes process variations and operating ranges by worst-case parameter sets. These sets are calculated adaptively during the sizing process based on sensitivity analyses. The method leads to robust designs with high parametric yield, while being much more efficient than design centering methods
Keywords
analogue integrated circuits; integrated circuit layout; integrated circuit yield; probability; sensitivity analysis; statistical analysis; adaptive worst-case parameter sets; analog IC design; analog circuit sizing; high parametric yield; nominal design; sensitivity analyses; Analog circuits; Circuit optimization; Delay estimation; Design automation; Design methodology; Integrated circuit technology; Integrated circuit yield; Production; Robustness; Sensitivity analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location
Paris
ISSN
1530-1591
Print_ISBN
0-7695-1471-5
Type
conf
DOI
10.1109/DATE.2002.998359
Filename
998359
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