• DocumentCode
    2456370
  • Title

    Improving placement under the constant delay model

  • Author

    Sulimma, Kolja ; Neumann, Ingmar ; VanGinneken, Lukas ; Kunz, Wolfgang

  • Author_Institution
    Dept. of Electr. Eng., Kaiserslautern Univ., Germany
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    677
  • Lastpage
    682
  • Abstract
    In this paper, we show that under the constant delay model the placement problem is equivalent to minimizing a weighted sum of wire lengths. The weights can be efficiently computed once in advance and still accurately reflect the circuit area throughout the placement process. The existence of an efficient and accurate cost function allows us to directly optimize circuit area. This leads to better results compared to heuristic edge weight estimates or optimization for secondary criteria such as wire length. We leverage this property to improve a recursive partitioning based tool flow. We achieve area savings of 27% for some circuits and 15% on average. The use of the constant delay model additionally enables timing closure without iterations
  • Keywords
    CMOS logic circuits; circuit layout; circuit optimisation; combinational circuits; delay estimation; integrated circuit layout; logic design; network topology; sequential circuits; CMOS gate; area savings; combinational circuits; constant delay model; minimisation; placement; recursive partitioning; sequential circuits; timing closure; tool flow; wire lengths; Capacitance; Circuits; Cost function; Delay effects; Design automation; Equations; Libraries; Semiconductor device modeling; Timing; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
  • Conference_Location
    Paris
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-1471-5
  • Type

    conf

  • DOI
    10.1109/DATE.2002.998372
  • Filename
    998372