An optimization algorithm for capacitor voltage balance of N-level Diode Clamped Inverters

Voltage balance of DC link capacitors is a problem in diode clamped multilevel inverters. In this work, a simple equivalent circuit, to predict the deviation of capacitor voltages for different operation modes, is presented. This model is used together with line voltage redundancy to develop an optimization algorithm to minimize the voltage deviation among different capacitors. This allows selecting the best switch combinations during each switching cycle to reach capacitors voltage balance. The algorithm is naturally applicable to converters with an arbitrary number of levels, regardless of the connection of primary voltage source to the DC bus. The performance of the proposed algorithm is evaluated by means of computer simulations.