A low cost FPGA image processor architecture with external line memory

Today´s FPGAs are capable of performing complex Image Processing schemes. For large images the limiting factor is the line memory required especially in lower cost FPGAs. In this paper we introduce a FPGA based architecture for Pipelined Image Processor that utilizes external line memory. We describe the suggested architecture, explain the reasoning behind it and give the guidelines to achieve the best efficiency possible. We define efficiency as performing the desired calculation with minimal hardware. Thus we give the tools to design minimal hardware configurations. The suggested architecture follows the principle of minimal data transportation between the external line memory and the FPGA.