An Efficient Architecture for Deblocking Filter in H.264/AVC

In this paper efficient hardware architecture for deblocking filter in H.264 is presented. A parallel filtering order is proposed without violating the standard, and the architecture is implemented in pipelined dataptah. With the parallel filtering order the vertical edges and horizontal edges can be processed simutaneously, and the filtering efficiency is improved. The memory is arranged and orgnized carefully, and data can be reused efficiently and memory reference is reduced. The architecture is implemented and verified on FPGA, and it takes only 116 clock cycle to process a 4:2:0 macroblock.