DocumentCode
2457204
Title
Arithematic for VLSI Signal Processing
Author
Swartzlander, Earl E., Jr.
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX
fYear
2006
fDate
Oct. 29 2006-Nov. 1 2006
Firstpage
899
Lastpage
906
Abstract
This paper presents a brief summary of some key algorithms for the implementation of digital signal processing systems that are suitable for realization via VLSI circuits. Examples of design approaches that are suitable for the implementation of fast adders, multipliers, and dividers are considered at the algorithm and logic design levels. Different algorithms may be used to vary the speed of an arithmetic element by an order of magnitude or more while the complexity varies by less than 50%.
Keywords
VLSI; adders; digital arithmetic; digital signal processing chips; dividing circuits; logic design; multiplying circuits; VLSI signal processing; adders; arithmetic element; digital signal processing system; dividers; logic design; multipliers; Signal processing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on
Conference_Location
Pacific Grove, CA
ISSN
1058-6393
Print_ISBN
1-4244-0784-2
Electronic_ISBN
1058-6393
Type
conf
DOI
10.1109/ACSSC.2006.354881
Filename
4176691
Link To Document