DocumentCode :
2457220
Title :
VLSI Architectures for JPEG 2000 EBCOT
Author :
Li, Yijun ; Bayoumi, Magdy
Author_Institution :
Center for Adv. Comput. Studies, Univ. of Louisiana at Lafayette, Lafayette, LA
fYear :
2006
fDate :
Oct. 29 2006-Nov. 1 2006
Firstpage :
907
Lastpage :
911
Abstract :
EBCOT tier-1, as entropy encoder of JPEG 2000, is a huge time-consuming part (typically more than 50%) and is considered a bottleneck for the entire system. In this paper, EBCOT tier-1 algorithm, including serial coding mode and parallel coding mode, is introduced. The VLSI architectures for EBCOT tier-1 can be divided into two categories: parallel bit-plane coding scheme (ParaBCS), where all bit-planes in a code block are coded in parallel, and serial bit-plane coding scheme (SeriBCS), where all bit-planes in a code-block are coded in serial. These two schemes are compared in terms of system throughput, PSNR performance, power consumption, and memory size. Finally, two case studies (one is based on SeriBCS and the other is based on ParaBCS) are presented.
Keywords :
VLSI; block codes; entropy codes; image coding; parallel algorithms; parallel architectures; JPEG 2000 EBCOT tier-1 algorithm; ParaBCS; SeriBCS; VLSI architecture; code block; entropy encoder; parallel bit-plane coding scheme; serial bit-plane coding scheme; Arithmetic; Computer architecture; Discrete wavelet transforms; Encoding; Energy consumption; Engines; Entropy; PSNR; Throughput; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
ISSN :
1058-6393
Print_ISBN :
1-4244-0784-2
Electronic_ISBN :
1058-6393
Type :
conf
DOI :
10.1109/ACSSC.2006.354882
Filename :
4176692
Link To Document :
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