Truncated Multiplication with Symmetric Correction

In the design of digital signal processing systems, where single-precision results are required, the power dissipation and area of parallel multipliers can be significantly reduced by truncating the less significant columns and compensating to produce an approximate rounded product. This paper provides a new method for truncated multiplication, which yields less errors than the previous methods with only slightly more complexity by a specialized counter. An error pattern is exhaustively analyzed with all possible inputs to evaluate the errors by the proposed correction method. Error and hardware comparisons of the previous methods and the proposed correction method are presented. The proposed method is applied to both unsigned and two´s complement multipliers.