Power-manageable scheduling technique for control dominated high-level synthesis

Author

Chen, Chunhong ; Sarrafzadeh, Majid

Author_Institution

Dept. of Electr. & Comput. Eng, Windsor Univ., Ont., Canada

fYear

2002

fDate

2002

Firstpage

1016

Lastpage

1020

Abstract

Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a given control-dominated data flow graph. We discuss delay and power issues with scheduling, and propose an improvement algorithm for insertion of so-called soft edges which enable power optimization under timing constraints. Power savings obtained by our approach on tested circuits range between 15 % and 30 % of the initial power dissipation

Keywords

data flow graphs; digital integrated circuits; high level synthesis; optimisation; power supply circuits; scheduling; timing; control-dominated data flow graph; high-level synthesis; power consumption optimization; power dissipation; power management; power savings; power scheduling; power-efficient digital system design; scheduled delays; soft edge insertion; timing constraints; Circuit testing; Constraint optimization; Delay; Design optimization; Digital systems; Energy consumption; Energy management; Flow graphs; Power system management; Scheduling algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

Conference_Location

Paris

ISSN

1530-1591

Print_ISBN

0-7695-1471-5

Type

conf

DOI

10.1109/DATE.2002.998424

Filename

998424