Title :
Bringing Network-on-Chip links to 45nm
Author :
Ferraresi, Marco ; Gobbo, Giuseppina ; Ludovici, Daniele ; Bertozzi, Davide
Author_Institution :
ENDIF, Univ. of Ferrara, Ferrara, Italy
fDate :
Oct. 31 2011-Nov. 2 2011
Abstract :
The literature lacks of a comprehensive overview of achievable NoC link performance when key parameters are swept in the link microarchitecture and in the NoC floorplan. This paper bridges this basic gap while at the same time capturing how link performance is affected by the migration from a 65nm to a 45nm technology node. Finally, it identifies the requirements on EDA tools to keep up with the technology scaling.
Keywords :
electronic design automation; network-on-chip; EDA tool; NoC floorplan; NoC link performance; electronic design automation; link microarchitecture; network-on-chip; size 45 nm; size 65 nm; Delay; Libraries; Pipeline processing; Repeaters; Routing; Switches; Wires;
Conference_Titel :
System on Chip (SoC), 2011 International Symposium on
Conference_Location :
Tampere
Print_ISBN :
978-1-4577-0671-4
Electronic_ISBN :
978-1-4577-0670-7
DOI :
10.1109/ISSOC.2011.6089686
