• DocumentCode
    2457722
  • Title

    Visualisation of partial order models in VLSI design flow

  • Author

    Bystrov, A. ; Yakovlev, A. ; Koutny, M.

  • Author_Institution
    Dept. of Comput. Sci., Newcastle upon Tyne Univ., UK
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    1089
  • Abstract
    Summary form only given. A new method, algorithms and tool for the visualisation of a finite complete prefix (FCP) of a Petri net (PN) or a signal transition graph are presented. A transformation is defined that converts such a prefix into a two-level model. At the top level, it has a finite state machine (FSM), describing modes of operation and transitions between them. At the low level, there are marked graphs, which can be drawn as waveforms, embedded into the top level nodes. The models of both levels are abstractions traditionally used by electronics engineers. The resultant model is completed trace equivalent to the original prefix. Moreover, the branching structure of the latter is preserved as much as possible
  • Keywords
    Petri nets; VLSI; circuit CAD; finite state machines; integrated circuit design; integrated circuit modelling; FSM; Petri net; VLSI design flow; branching structure; finite complete prefix; finite state machine; marked graphs; model visualisation; partial order models; signal transition graph; transformation; two-level model; Automata; Clocks; Concurrent computing; Electromagnetic compatibility; Energy consumption; Power engineering and energy; Robustness; Timing; Very large scale integration; Visualization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
  • Conference_Location
    Paris
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-1471-5
  • Type

    conf

  • DOI
    10.1109/DATE.2002.998446
  • Filename
    998446