Low-power arithmetic unit for DSP applications

DSP algorithms are one of the most important components of modern embedded computer systems. These applications generally include fixed point and floating-point arithmetic operations and trigonometric functions which have long latencies and high power consumption. Nonetheless, DSP applications enjoy from some interesting characteristics such as tolerating slight loss of accuracy and high degree of value locality which can be exploited to improve their power consumption and performance. In this paper, we present an application-specific result-cache that aims to reduce the power consumption and latency of DSP algorithms by reusing the results of the arithmetic operations executed on the same (or approximately the same) inputs. Our proposal improves the area overhead and hit ratio of previously proposed result-caches by figuring out the frequent operands of the arithmetic operations and allocating the cache entries to them. This mechanism exploits the fact that in most DSP applications, one of the operands of the arithmetic operations is input-data independent and takes its value from a finite set of coefficients. The experimental results show that the proposed approach can significantly reduce the power consumption of arithmetic operations by providing a high hit ratio using a small cache.