Title :
Design methodology to distribute on-chip power in next generation integrated circuits
Author :
Köse, Selçuk ; Friedman, Eby G.
Author_Institution :
Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
Abstract :
The performance of an integrated circuit depends strongly upon the power delivery network. With the introduction of ultra-small on-chip voltage regulators, novel design methodologies are needed to determine the location of these on-chip power supplies and decoupling capacitors. In this paper, the optimal location of the power supplies and decoupling capacitors is determined for different size and number of components. Optimization algorithms widely used for facility location problems are applied in the proposed methodology. The effect of the size, number, and location of the power supplies and decoupling capacitors on the power noise is also discussed.
Keywords :
capacitors; integrated circuit design; optimisation; power supply circuits; voltage regulators; decoupling capacitors; design methodology; facility location problems; next generation integrated circuits; on-chip power supplies; optimal location; optimization algorithms; power noise; ultra-small on-chip voltage regulators; Capacitors; Optimization; Power supplies; Regulators; System-on-a-chip; Voltage control;
Conference_Titel :
Electrical & Electronics Engineers in Israel (IEEEI), 2012 IEEE 27th Convention of
Conference_Location :
Eilat
Print_ISBN :
978-1-4673-4682-5
DOI :
10.1109/EEEI.2012.6377093
