DocumentCode
2457858
Title
Control circuit templates for asynchronous bundled-data pipelines
Author
Tugsiriavisut, S. ; Beerel, Peter A.
Author_Institution
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
fYear
2002
fDate
2002
Firstpage
1098
Abstract
This paper proposes the use of templatized asynchronous control circuits with single-rail datapaths to create low-power bundled-data non-linear pipelines. First, we adapt an existing templatized control style for 1-of-N rail pipelines, the Pre-Charged Full Buffer PCFB, to bundled-data pipelines. Then, we present a novel true 4-phase template (T4PFB) that has lower control overhead. Simulation results indicate 12%-44% higher throughput for the pipeline stage equivalent to 8 to 40 gates
Keywords
asynchronous circuits; buffer circuits; low-power electronics; pipeline processing; control circuit template; low-power asynchronous bundled-data nonlinear pipeline; pre-charged full buffer; single-rail datapath; true four-phase full buffer; Asynchronous circuits; Circuit simulation; Clocks; Control systems; Coupling circuits; Delay lines; Error correction; Pipelines; Rails; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location
Paris
ISSN
1530-1591
Print_ISBN
0-7695-1471-5
Type
conf
DOI
10.1109/DATE.2002.998454
Filename
998454
Link To Document