DocumentCode
2457875
Title
Transforming arbitrary structures into topologically equivalent slicing structures
Author
Peyran, Olivier ; Zhuang, Wenjun
Author_Institution
Inst. of High Performance Comput., Singapore, Singapore
fYear
2002
fDate
2002
Firstpage
1099
Abstract
Floorplanning is an important step of IC design. Traditionally, floorplan representation has been segregated between slicing and non-slicing structures. We present a heuristic that translates any arbitrary structure into a slicing one, topologically equivalent to the initial one after a 1-D compaction
Keywords
VLSI; circuit layout CAD; circuit optimisation; equivalent circuits; integrated circuit layout; network topology; 1D compaction; IC design; arbitrary structures; circuit optimisation; floorplan representation; floorplanning; heuristic; topologically equivalent slicing structures; very deep sub micron technologies; Automatic testing; Circuit optimization; Compaction; Design automation; Europe; Extremities; High performance computing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location
Paris
ISSN
1530-1591
Print_ISBN
0-7695-1471-5
Type
conf
DOI
10.1109/DATE.2002.998455
Filename
998455
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