• DocumentCode
    2457889
  • Title

    A new formulation for SOC floorplan area minimization problem

  • Author

    Lee, Chih-Hung ; Lin, Yu-Chung ; Wen-Yu-Fu ; Chang, Chun-Chiao ; Hsieh, Tsai-Ming

  • Author_Institution
    Dept. of Electron. Eng., Chung Yuan Christian Univ., Chung-li, Taiwan
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    1100
  • Abstract
    Presented a new formulation by introducing the concept of block partition such that the shape of modules can be automatically determined based on the goal of optimization. Experimental results from MCNC benchmarks indicate that the zero dead space solutions can be obtained for most test cases under our formulation
  • Keywords
    VLSI; application specific integrated circuits; circuit layout CAD; integrated circuit layout; logic CAD; logic partitioning; minimisation of switching nets; modules; wiring; MCNC benchmarks; SOC; VLSI; block partition; critical nets; floorplan area minimization; inter-module wire length; modules; nonlinear programming; optimization; zero dead space solutions; Automatic testing; Design automation; Europe;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
  • Conference_Location
    Paris
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-1471-5
  • Type

    conf

  • DOI
    10.1109/DATE.2002.998456
  • Filename
    998456
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2457889