Title :
Implementation of AES algorithm on FPGA for low area consumption
Author :
Khose, Pritamkumar N. ; Raut, Vrushali G.
Author_Institution :
Dept. of Electron. & Telecommun., Sinhgad Coll. of Eng., Pune, India
Abstract :
An AES algorithm can be implemented in software or hardware but hardware implementation is more suitable for high speed applications in real time. AES is most secure security algorithm to maintain safety and reliability of data transmission. The main goal of paper is AES hardware implementation to achieve less area and low power consumption which maintain standard throughput of data, also to achieve high speed data processing and reduce time for key generating. AES hardware implementation can easily reset and immediately erase data on disk. The conventional Sbox combinational logic is replaced by BRAM which gives instantaneous output. The AES 128/196/256 is implements on a FPGA using HDL language with help of Xilinx ISE tool.
Keywords :
circuit reliability; combinational circuits; cryptography; field programmable gate arrays; AES algorithm; BRAM; FPGA; HDL language; Sbox combinational logic; VHSIC; Xilinx ISE tool; advanced encryption standard; data transmission reliability; data transmission safety; field programmable gate array; high speed data processing; low area consumption; low power consumption; security algorithm; standard data throughput; time reduction; Ciphers; Computer architecture; Encryption; Hardware; Standards; Throughput; Advanced Encryption Standard (AES); Field Programmable Gate Array (FPGA); VHSIC Hardware Description Language (VHDL);
Conference_Titel :
Pervasive Computing (ICPC), 2015 International Conference on
Conference_Location :
Pune
DOI :
10.1109/PERVASIVE.2015.7087102