Automated Hardware IP Generation for Digital Signal Processing Applications

This paper presents a design environment for efficiently generating application-specific finite impulse response (FIR) filters. We used the FIR filters blocks to construct signal processing hardware systems . Our design and performance analysis framework (D-PAF) significantly reduced the design efforts by providing low-level optimization techniques implemented from a higher level of design abstraction. We used a three-level, five-channel discrete wavelet transform (DWT) system as a case study to illustrate that our framework generated improved FIR filters. These filter structures can be used to improve the overall system performance compared to the use of general purpose FIR intellectual property (IP) cores. We exhibited a 33% increase in throughput using our efficient FIR filters while reducing the overall design size by half. Design and analysis times are in the order of minutes using our framework, versus weeks or months using conventional design methods.