Title :
Optimized Viterbi Decoder for Low Data Rate Systems
Author :
Bianchi, D. ; Cardarilli, G.C. ; Del Re, A. ; Re, A. Del
Author_Institution :
Dept. of Electr. Eng., Univ. of Roma Tor Vergata, Rome
fDate :
Oct. 29 2006-Nov. 1 2006
Abstract :
In this paper an optimized architecture of a Viterbi decoder is proposed, thought for low data rate systems, such as reliable control signaling and power line communications. Particular attention has been paid to reduce the amount of memory required to store path metrics. In order to prove the efficiency of the proposed architecture, a 64-states decoder has been implemented on FPGA. The gain with respect to the un-coded modulation has been evaluated for both 32-TCM and 128-TCM transmission. An accurate tuning of the trellis length and path metrics approximation has been carried out to obtain the best trade-off between area and performance.
Keywords :
Viterbi decoding; carrier transmission on power lines; data communication; field programmable gate arrays; trellis coded modulation; FPGA; Viterbi decoder; control signaling; low data rate systems; optimized decoder; path metrics approximation; power line communications; trellis length tuning; uncoded modulation; Convolutional codes; Data engineering; Delay; Euclidean distance; Hidden Markov models; Maximum likelihood decoding; Power system reliability; Quadrature amplitude modulation; Sequences; Viterbi algorithm;
Conference_Titel :
Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
1-4244-0784-2
Electronic_ISBN :
1058-6393
DOI :
10.1109/ACSSC.2006.354938
