• DocumentCode
    2458353
  • Title

    An evolutionary approach to the design of on-chip pseudorandom test pattern generators

  • Author

    Favalli, Michele ; Dalpasso, Marcello

  • Author_Institution
    Ferrara Univ., Italy
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    1122
  • Abstract
    Summary form only given. Weighted pseudorandom test generation (WPRTG) uses test sequences characterized by non-uniform distributions of test vectors in order to increase the detection probability of random resistant faults. Such non-uniform distributions are characterized by the values of signal probability of the CUT inputs (weights). Since different faults may require different distributions, a (small) number of distributions is typically used. The weights of such distributions are identified by analyzing the CUT The corresponding pseudorandom sequences are typically obtained by inserting a combinational network between the TPG and the CUT. Differently from the genetic-based approaches, where only numerical coefficients are computed, we have used an evolutionary programming (EP) algorithm that directly evolves the WGU network. In fact, evolutionary approaches have been shown to be effective in the design of digital circuits. In particular, we evolve a population were each individual represents a possible WGU and the fitness function considers the fault coverage as a primary target and the test length and the cost of the WGU as secondary ones. The fault coverage is evaluated here by means of fault simulation
  • Keywords
    automatic test pattern generation; built-in self test; combinational circuits; evolutionary computation; fault simulation; integrated circuit testing; logic design; logic testing; ATPG; BIST; CUT inputs; WGU network; combinational network; detection probability; digital circuits; evolutionary programming algorithm; fault coverage; fault simulation; fitness function; on-chip pseudorandom TPG; pseudorandom test pattern generators; random resistant faults; signal probability; test sequence optimisation; test vectors nonuniform distributions; weighted pseudorandom test generation; Character generation; Circuit faults; Circuit simulation; Circuit testing; Computer networks; Cost function; Digital circuits; Fault detection; Genetic programming; Random sequences;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
  • Conference_Location
    Paris
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-1471-5
  • Type

    conf

  • DOI
    10.1109/DATE.2002.998478
  • Filename
    998478