Title :
A heuristic for test scheduling at system level
Author :
Flottes, Marie-Lise ; Pouget, Julien ; Rouzeyre, Bruno
Author_Institution :
LIRMM, Univ. of Montpellier, France
Abstract :
Summary form only given. This paper considers the test-scheduling problem of a SoC. The proposed approach is based on a "sessionless" test scheme. It minimizes the system test time while respecting a power dissipation limit and test resource sharing constraints. Experimental results show that our approach outperforms other related test scheduling solutions
Keywords :
VLSI; application specific integrated circuits; automatic testing; integrated circuit testing; scheduling; SoC testing; VLSI; power constrained test scheduling algorithm; power dissipation limit; sessionless test scheme; system test time minimisation; system-on-a-chip testing; test resource sharing constraints; test-scheduling problem; Clocks; Costs; Electronic switching systems; Parallel processing; Power dissipation; Processor scheduling; System testing;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-7695-1471-5
DOI :
10.1109/DATE.2002.998480
