A novel methodology for the concurrent test of partial and dynamically reconfigurable SRAM-based FPGAs

Author

Gericota, Manuel G. ; Alves, Gustavo R. ; Silva, Miguel L. ; Ferreira, José M.

Author_Institution

Dept. of Electr. Eng., ISEP, Porto, Portugal

fYear

2002

fDate

2002

Firstpage

1126

Abstract

This paper presents the first truly non-intrusive structural concurrent test approach, aimed to test partial and dynamically reconfigurable SRAM-based FPGAs without disturbing their operation. This is accomplished by using a new methodology to carry out the replication of active configurable logic blocks (CLBs), i.e. CLBs that are part of an implemented function that is actually being used by the system, releasing it to be tested in a way that is completely transparent to the system

Keywords

SRAM chips; concurrent engineering; field programmable gate arrays; integrated circuit testing; logic testing; reconfigurable architectures; active configurable logic block replication; concurrent test methodology; dynamically reconfigurable SRAM-based FPGAs; implemented function blocks; nonintrusive structural concurrent test; partially reconfigurable SRAM-based FPGAs; Concurrent computing; Fault tolerant systems; Field programmable gate arrays; Hardware; Life testing; Manufacturing; Pins; Reconfigurable logic; Runtime; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

Conference_Location

Paris

ISSN

1530-1591

Print_ISBN

0-7695-1471-5

Type

conf

DOI

10.1109/DATE.2002.998482

Filename

998482