Title :
Mappability estimation of architecture and algorithm
Author :
Soininen, Juha-Pekka ; Kreku, Jari ; Qu, Yang
Author_Institution :
VTT Electron., Oulu, Finland
Abstract :
Method for the selection of processor core and algorithm combinations for system on chip designs is presented. The method uses a mappability concept that is an addition to performance and cost metrics used in codesign. The mappability estimation is based on the analysis of the correlations of algorithm and core characteristics. The method is demonstrated with an analysis tool and the experimental results with DSP cores and algorithms are similar to expectations
Keywords :
circuit CAD; digital signal processing chips; integrated circuit design; DSP; algorithm-architecture mappability; processor core; system-on-chip design; Algorithm design and analysis; Computational modeling; Computer architecture; Costs; Digital signal processing; Finite impulse response filter; Hardware; Performance analysis; System-on-a-chip; Wireless LAN;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-7695-1471-5
DOI :
10.1109/DATE.2002.998488
