A parallel LCC simulation system

Author

Hering, Klaus

Author_Institution

Dept. of Comput. Sci., Chemnitz Univ. of Technol., Germany

fYear

2002

fDate

2002

Firstpage

1134

Abstract

Cycle-based simulation at RT- and gate level realized by a Levelized Compiled Code (LCC) technique represents a well established method for functional verification in processor design. We present a parallel LCC simulation system developed to run on loosely-coupled processor systems allowing significant simulation acceleration. It comprises three parallel simulators and a complex model partitioning environment. A key idea of our approach is to valuate circuit model partitions with respect to the expected parallel simulation run-time and to integrate corresponding cost functions into partitioning algorithms. Experimental results are given with respect to IBM processor models of different size

Keywords

circuit CAD; circuit simulation; formal verification; integrated circuit design; microprocessor chips; parallel algorithms; RT-level; circuit model; cost function; cycle-based simulation; functional verification; gate level; levelized compiled code; parallel LCC simulation system; partitioning algorithm; processor design; Chemical technology; Circuit simulation; Computational modeling; Computer science; Computer simulation; Cost accounting; Logic; Partitioning algorithms; Process design; Runtime;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

Conference_Location

Paris

ISSN

1530-1591

Print_ISBN

0-7695-1471-5

Type

conf

DOI

10.1109/DATE.2002.998492

Filename

998492