Title :
Machine-learning-based circuit synthesis
Author :
Rokach, Lior ; Feldman, Alexander ; Kalech, Meir ; Provan, Gregory
Author_Institution :
Ben Gurion Univ., Ben Gurion, Israel
Abstract :
Multi-level logic synthesis is a problem of immense practical significance, and is a key to developing circuits that optimize a number of parameters, such as depth, energy dissipation, reliability, etc. The problem can be defined as the task of taking a collection of components from which one wants to synthesize a circuit that optimizes a particular objective function. This problem is computationally hard, and there are very few automated approaches for its solution. To solve this problem we propose an algorithm, called Circuit-Decomposition Engine (CDE), that is based on learning decision trees, and uses a greedy approach for function learning. We empirically demonstrate that CDE, when given a library of different component types, can learn the function of Disjunctive Normal Form (DNF) Boolean representations and synthesize circuit structure using the input library. We compare the structure of the synthesized circuits with that of well-known circuits using a range of circuit similarity metrics.
Keywords :
Boolean functions; decision trees; electronic engineering computing; greedy algorithms; learning (artificial intelligence); logic design; multivalued logic; CDE; DNF Boolean representations; circuit decomposition engine; circuit similarity metrics; components collection; developing circuits; disjunctive normal form Boolean representations; function learning; greedy approach; learning decision trees; machine learning-based circuit synthesis; multilevel logic synthesis; objective function; Adders; Algorithm design and analysis; Boolean functions; Decision trees; Educational institutions; Libraries; Logic gates;
Conference_Titel :
Electrical & Electronics Engineers in Israel (IEEEI), 2012 IEEE 27th Convention of
Conference_Location :
Eilat
Print_ISBN :
978-1-4673-4682-5
DOI :
10.1109/EEEI.2012.6377134