DocumentCode
245887
Title
Fast Protocol Decoding in Parallel with FPGA Hardware
Author
Han Li ; Yuzhuo Fu ; Ting Liu ; Jiafang Wang
Author_Institution
Shanghai Jiao Tong Univ., Shanghai, China
fYear
2014
fDate
19-21 Dec. 2014
Firstpage
1669
Lastpage
1673
Abstract
Current studies about decoding Fast protocol in the FPGA platform are always implemented using serial communication technique and for some certain Fast Templates. This paper presents the FPGA hardware design of accelerating the decoding process in parallel and cutting down the cost of changing Fast Templates with flexible decoders. The complete system has been simulated and tested in SystemC Platform.
Keywords
decoding; field programmable gate arrays; logic design; parallel processing; protocols; FPGA hardware design; SystemC platform; fast protocol decoding process; fast templates; flexible decoders; parallel decoding process; serial communication technique; Bandwidth; Decoding; Educational institutions; Field programmable gate arrays; Hardware; Protocols; Registers; FPGA; Fast protocol; SystemC; in parallel;
fLanguage
English
Publisher
ieee
Conference_Titel
Computational Science and Engineering (CSE), 2014 IEEE 17th International Conference on
Conference_Location
Chengdu
Print_ISBN
978-1-4799-7980-6
Type
conf
DOI
10.1109/CSE.2014.307
Filename
7023818
Link To Document