Synthesis and Implementation of UART Using VHDL Codes

The proposed paper describes the universal asynchronous receiver/transmitter i.e. UART which is the kind of serial communication protocol which allows the full duplex communication in serial link. This paper presents the hardware implementation of a high speed and efficient UART using FPGA. The UART consists of three main components namely transmitter, receiver and baud rate generator which is nothing but the frequency divider. This has been simulated on ModelSim SE 10.0a and has been implemented by using Verilog description language which has been synthesized on FPGA kits such as Virtex4 and Spartan3.