Title :
Multi-million gate FPGA physical design challenges
Author :
Maogang Wang ; Ranjan, Abhishek ; Raje, Salil
Author_Institution :
Cadence Design Syst., San Jose, CA, USA
Abstract :
The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. These large design sizes significantly impact cycle time due to design automation software runtimes and an increased number of performance based iterations. New FPGA physical design approaches need to be utilized to alleviate some of these problems. Hierarchical approaches to divide and conquer, the design, early estimation tools for design exploration, and physical optimizations are some of the key methodologies that have to be introduced in the FPGA physical design tools. This paper will investigate the loss/benefit in quality of results due to hierarchical approaches and compare and contrast some of the design automation problem formulations and solutions needed for FPGAs versus known standard cell ASIC approaches.
Keywords :
application specific integrated circuits; field programmable gate arrays; integrated circuit design; application specific integrated circuits; design automation; design circuits; field programmable gate arrays; multimillion gate FPGA physical design; standard cell ASIC; Application specific integrated circuits; Assembly; Clocks; Delay estimation; Design automation; Design optimization; Field programmable gate arrays; Integrated circuit interconnections; Runtime; Software performance;
Conference_Titel :
Computer Aided Design, 2003. ICCAD-2003. International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
1-58113-762-1
DOI :
10.1109/ICCAD.2003.159780