DocumentCode :
245982
Title :
Lessons from Experimental Methodology of Cache Hierarchy Changes with the Memory Technology
Author :
Yanjiang Wei ; Rui Wang ; Danfeng Zhu ; Zhongzhi Luan ; Depei Qian
Author_Institution :
Sch. of Comput. Sci. & Eng., Beihang Univ., Beijing, China
fYear :
2014
fDate :
19-21 Dec. 2014
Firstpage :
1953
Lastpage :
1959
Abstract :
Caching is an important technique to improve computer system performance by storing the most recently used data and instructions for main memory. Cache is widely used in modern computer systems and will continue to be an irreplaceable unit to narrow the speed gap between processor and main memory. With the increasing capacity of main memory and the number of processor cores, the cache technology has great development. In this paper, we have some lessons of cache hierarchy changes with the memory technology from experimental methodology. We design a serial of experiments and try to answer some questions about cache designs. Our experiments results indicate that more levels of cache does not necessarily means better performance for all benchmarks, that last level cache miss rate has no direct connection with the system performance, that the average performance of exclusive cache hierarchy is more effective than that of inclusive cache.
Keywords :
cache storage; microprocessor chips; cache design; cache hierarchy changes; cache miss rate; cache technology; caching; computer system performance; memory technology; processor core; Benchmark testing; Cache memory; Computers; Correlation; Memory management; Phase change materials; System performance; Cache memory; Cache miss rate; Exclusive cache; Last level cache; Multi-level cache;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computational Science and Engineering (CSE), 2014 IEEE 17th International Conference on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4799-7980-6
Type :
conf
DOI :
10.1109/CSE.2014.357
Filename :
7023869
Link To Document :
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