DocumentCode :
2459939
Title :
Source/drain engineering for sub 100-nm technology node
Author :
Ohuchi, Kouji ; Adachi, Koichiro ; Hokazono, A. ; Toyoshima, Yoshiaki
fYear :
2002
fDate :
27-27 Sept. 2002
Firstpage :
7
Lastpage :
12
Abstract :
ITRS2001 indicates 25-nm physical gate length and 10-17-nm extension depth are required in 65-nm technology node for high performance application. It means resultant requirement of precisely controlled conventional process and new material and process introduction. Though ion implantation and spike RTA are still base line technology for doping, it should be carefully optimized in process integration avoiding implantation-induced damage and transient enhanced diffusion. Careless process sequence might cause undesired enlargement of junction depth even in LPCVD temperature annealing. Sidewall scaling is also necessary to reduce source and drain parasitic resistance and it relates to the contact junctions and silicidation process. Cobalt salicide is widely used in recent technology node. However, its silicon consumption in silicidation process requires relatively deep contact junctions and tends to cause the interference of the contact junction to the channel region. Therefore, lower silicon consumption silicide material such as nickel SALICIDE is one of the solutions. NiSi silicidation can be performed at low temperature and silicon consumption is about 80% of CoSi2 silicide under the same silicide thickness condition. Additionally, more structural approach like elevated source/drain using selective silicon or silicon-germanium will be introduced to solve severer constraints.
Keywords :
CMOS integrated circuits; CVD coatings; MOSFET; ion implantation; nanotechnology; rapid thermal annealing; semiconductor doping; 10 to 17 nm; 10-17-nm extension depth; 25 nm; 25-nm physical gate length; 65 nm; 65-nm technology node; ITRS2001; LPCVD temperature annealing; Sidewall scaling; base line technology; contact junctions; doping; ion implantation; junction depth enlargement; nickel SALICIDE; parasitic resistance; process integration avoiding implantation-induced damage; silicidation process; source/drain engineering; spike RTA; sub 100-nm technology node; transient enhanced diffusion; Annealing; Cobalt; Contact resistance; Doping; Ion implantation; Process control; Silicidation; Silicides; Silicon; Temperature;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on
Conference_Location :
Taos, New Mexico, USA
Print_ISBN :
0-7803-7155-0
Type :
conf
DOI :
10.1109/IIT.2002.1257925
Filename :
1257925
Link To Document :
بازگشت