VLSI block placement with directional graphs based on the new non-slicing representation

This paper describes a novel non-slicing floorplan representation. The designed representation of blocks differ from existing ones for low requirements allocated to the volume of the memory used. The time required to decode a representation, i.e. construction of its layout, is O(n). The described operations of conversion of the structure of a graph of representation is utilized in a genetic algorithm. The transparency of the geometrical relationships for the operations of conversion of the graph makes finding the final decision more effective.