DocumentCode :
2460376
Title :
VLSI block placement with directional graphs based on the new non-slicing representation
Author :
Kovalev, A.V. ; Konoplev, B.G.
Author_Institution :
Taganrog State Radio Eng. Univ., Russia
fYear :
2002
fDate :
2002
Firstpage :
414
Lastpage :
417
Abstract :
This paper describes a novel non-slicing floorplan representation. The designed representation of blocks differ from existing ones for low requirements allocated to the volume of the memory used. The time required to decode a representation, i.e. construction of its layout, is O(n). The described operations of conversion of the structure of a graph of representation is utilized in a genetic algorithm. The transparency of the geometrical relationships for the operations of conversion of the graph makes finding the final decision more effective.
Keywords :
VLSI; circuit layout CAD; genetic algorithms; graph theory; integrated circuit layout; VLSI block placement; block representation; directional graphs; genetic algorithm; geometrical relationships; nonslicing floorplan representation; Artificial intelligence; Clustering algorithms; Decoding; Floors; Genetic algorithms; Tree graphs; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Artificial Intelligence Systems, 2002. (ICAIS 2002). 2002 IEEE International Conference on
Print_ISBN :
0-7695-1733-1
Type :
conf
DOI :
10.1109/ICAIS.2002.1048149
Filename :
1048149
Link To Document :
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