Comparison of Montgomery and Barrett modular multipliers on FPGAs

Author

Kong, Yinan ; Phillips, Braden

Author_Institution

Centre for High Performance Integrated Technol. & Syst. (CHiPTec) Sch. of Electr. & Electron. Eng., Univ. of Adelaide, Adelaide, SA

fYear

2006

fDate

Oct. 29 2006-Nov. 1 2006

Firstpage

1687

Lastpage

1691

Abstract

A diverse variety of algorithms and architectures for modular multiplication have been published. This paper concentrates on 2 algorithms, Montgomery and Barrett, and provides area and timing results for FPGA implementations of different architectures and wordlengths. The results show that techniques such as quotient pipelining and trivial quotient digit selection are not well suited to FPGA implementations, but that high-radix, separated modular multipliers perform well on this platform.

Keywords

digital arithmetic; field programmable gate arrays; multiplying circuits; pipeline processing; Barrett modular multipliers; FPGA; Montgomery modular multipliers; quotient pipelining; trivial quotient digit selection; Australia; Computer architecture; Cryptography; Delay; Digital arithmetic; Field programmable gate arrays; Image processing; Logic; Pipeline processing; Timing; FPGA; computer arithmetic; modular multiplication;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

1-4244-0784-2

Electronic_ISBN

1058-6393

Type

conf

DOI

10.1109/ACSSC.2006.355048

Filename

4176858