DocumentCode :
2460510
Title :
Comparison of binary full adder and quaternary signed-digit full adder using high-speed ECL
Author :
Wakui, Fumio ; Tanaka, Masaichi
Author_Institution :
Dept. of Electron. Eng., Nihon Univ., Chiba, Japan
fYear :
1989
fDate :
29-31 May 1989
Firstpage :
346
Lastpage :
355
Abstract :
Details are presented of the algorithm and the several circuits needed to construct a novel emitter-coupled logic (ECL) quaternary signed-digit full adder (SDFA4) to realize high-speed operation under restrained power dissipation. To reduce the circuit size, the input part of the SDFA4 which converts the sums of input currents to voltage signals, detects the signs of the sums. The output part, which has the unsigned transfer characteristic, selects output lines corresponding to the signs. To increase the maximum number of realizable thresholds under the restrained supply voltage of the ECL, a signal distributor was used. The SDFA4 performance is compared to that of a 4-b carry-lookahead full adder
Keywords :
adders; emitter-coupled logic; SDFA4; binary full adder; high-speed ECL; quaternary signed-digit full adder; unsigned transfer characteristic; Adders; Circuits; Computer aided manufacturing; Educational institutions; Equations; Manufacturing processes; Power dissipation; Power engineering and energy; Signal detection; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multiple-Valued Logic, 1989. Proceedings., Nineteenth International Symposium on
Conference_Location :
Guangzhou
Print_ISBN :
0-8186-1947-3
Type :
conf
DOI :
10.1109/ISMVL.1989.37805
Filename :
37805
Link To Document :
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