Power and Area Efficient Squarer Design

The partial product matrix (PPM) of a parallel squarer is symmetric. To reduce the depth of PPM, it can be folded, shifted and rearranged. In this paper, we present a high performance parallel squarer design method. Also, a fixed-width squarer design method of the proposed squarer is presented. By simulations, it is shown that the proposed squarers lead to up to 17% reduction in area, 10% reduction in propagation delay and 10% reduction in power consumption compared with previous squarers. By using the proposed fixed-width squarers, the area, propagation delay and power consumption can be further reduced up to 30%, 16% and 28%, respectively.