Title :
Parallelization of DVFS-enabled H.264/AVC Decoder on Heterogeneous Multi-core Platform
Author :
Lu, Yu-Sheng ; Lai, Chin-Feng ; Huang, Yueh-Min
Author_Institution :
Dept. of Eng. Sci., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
Using a multi-core system to process real-time data of high computational complexity has become a popular solution for effectively enhancing system processing efficiency. However, the high-power consumption of a multi-core system remains a problem, particularly to handheld devices. Applying DVFS to properly decrease the system voltage and frequency can effectively save system power loss, nevertheless, the question of how to effectively and accurately configure a dynamic DVFS system to avoid missing a deadline or extra power loss remains to be widely discussed. This study examines many previous parallel processing architectures and DVFS mechanisms, and proposes two different orientations of parallel DVFS-enabled H.264/AVC decoders, and implements a multimedia heterogeneous multi-core platform. Based on experimental data, the impact of two parallel DVFS-able processing systems on H.264 decoding performance and power loss are studied.
Keywords :
computational complexity; decoding; multimedia systems; multiprocessing systems; parallel architectures; power aware computing; video coding; DVFS-enabled H.264/AVC decoder parallelization; H.264 decoding performance; computational complexity; dynamic DVFS system; high-power consumption; multimedia heterogeneous multicore platform; parallel processing architectures; real-time data processing; system frequency reduction; system power loss saving; system processing efficiency enhancement; system voltage reduction; Computers; DVFS; H.264/AVC Decoder; Heterogeneous Multicore Platform;
Conference_Titel :
Computer, Consumer and Control (IS3C), 2012 International Symposium on
Conference_Location :
Taichung
Print_ISBN :
978-1-4673-0767-3
DOI :
10.1109/IS3C.2012.48
