DocumentCode
2460917
Title
The Gauss machine: A Galois-enhanced quadratic residue number system systolic array
Author
Mellott, Jonathon D. ; Smith, Jeremy C. ; Taylor, Fred J.
Author_Institution
High Speed Digital Archit. Lab., Florida Univ., FL, USA
fYear
1993
fDate
29 Jun-2 Jul 1993
Firstpage
156
Lastpage
162
Abstract
The Gauss machine is a SIMD systolic array architecture that takes advantage of the Galois-enhanced residue number system (GEQRNS) to form reduced-complexity arithmetic elements. The Gauss machine is targeted at front-end signal and image processing applications. A discrete prototype that achieves a peak rating of 320 million complex arithmetic operations per second while operating at 10 MHz has been constructed. A VLSI implementation of the Gauss machine´s processor cell has been created. The VLSI implementation is implemented in 2.0-μm CMOS and achieves greater than 20-MHz performance, using less than 2.0-mm2 die area. It is shown that techniques for defect tolerance in RNS systolic arrays can result in substantial yield enhancement, thereby making larger than conventional (ULSI) systems possible
Keywords
residue number systems; systolic arrays; Galois-enhanced; Gauss machine; SIMD systolic array architecture; defect tolerance; quadratic residue number system; reduced-complexity arithmetic; systolic array; Adders; Digital arithmetic; Gaussian processes; Laboratories; Power system reliability; Prototypes; Signal processing; Systolic arrays; Ultra large scale integration; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Arithmetic, 1993. Proceedings., 11th Symposium on
Conference_Location
Windsor, Ont.
Print_ISBN
0-8186-3862-1
Type
conf
DOI
10.1109/ARITH.1993.378097
Filename
378097
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