CONCORD II: A Configurable SoC Prototyping Platform

The present SoC prototyping platforms in the market are usually with stationary connecting architecture, including designated bus protocols and peripheral interfaces. Due to the lack of architectural flexibility, users are not allowed to adapt the architecture for specific applications by on-chip-buses and on-chip-networks. In addition, the system architecture under the FPGA-based SoC may differ from the real chip. In our previous work, a configurable SoC prototyping platform, namely, CONCORD, was proposed to provide high flexibility, compatibility, and modularity in connection interfaces, for demands from various applications. In this paper, an improved version, named CONCORD II, is proposed. In contrast to CONCORD, CONCORD II operates with higher clock rate, greater FPGA capacity, more types of transmission signals, and additional categories of peripheral sub-modules.