Optimization of AVS-M Video Decoder for Real-time Implementation on Embedded RISC Processors

Author

Jian, Guo-An ; Chu, Jui-Chin ; Guo, Jiun-In

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan

fYear

2009

fDate

12-14 Sept. 2009

Firstpage

98

Lastpage

101

Abstract

In this paper, we propose a powerful AVS-M video decoder that can perform real-time decoding of AVS-M video on embedded RISC processors. Our optimization schemes cover algorithmic improvement, zero skipping, early termination, and data reusing. We have reduced about 90%~93% of complexity after optimization with the proposed techniques as compared to the original reference codes. The proposed low complexity AVS-M video decoder can achieve about QVGA@30 fps~50 fps when running on ARM920T processor at 384 MHz.

Keywords

microprocessor chips; optimisation; reduced instruction set computing; video coding; ARM920T processor; AVS-M video decoder; algorithmic improvement; data reusing; early termination; embedded RISC processors; optimization schemes; zero skipping; Application software; Computational complexity; Decoding; Entropy; Interpolation; Motion compensation; Quantization; Reduced instruction set computing; Software algorithms; Video signal processing; software optimization;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent Information Hiding and Multimedia Signal Processing, 2009. IIH-MSP '09. Fifth International Conference on

Conference_Location

Kyoto

Print_ISBN

978-1-4244-4717-6

Electronic_ISBN

978-0-7695-3762-7

Type

conf

DOI

10.1109/IIH-MSP.2009.199

Filename

5337309