• DocumentCode
    2461275
  • Title

    Two-staged Tabu Search for Floorplan Problem Using O-Tree Representation

  • Author

    Ninomiya, Hiroshi ; Numayama, Kimihiko ; Asai, Hideki

  • Author_Institution
    Shonan Inst. of Technol., Fujisawa
  • fYear
    0
  • fDate
    0-0 0
  • Firstpage
    718
  • Lastpage
    724
  • Abstract
    This paper describes the two-staged Tabu search for the non-slicing floorplan problem using the ordered tree representation called O-tree. The floorplan problem is a part of VLSI layout design problem. Furthermore, we combine ideas from the simulated annealing into the two-staged Tabu search and propose a novel hybrid algorithm for floorplan represented by O-tree. Finally, we demonstrate the validity of two-staged search and hybrid method for MCNC benchmark tests through the computer simulations.
  • Keywords
    VLSI; integrated circuit layout; search problems; simulated annealing; trees (mathematics); MCNC benchmark tests; O-tree representation; VLSI layout design problem; floorplan problem; ordered tree representation; simulated annealing; two-staged Tabu search; Benchmark testing; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Helium; Simulated annealing; Space technology; Very large scale integration; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Evolutionary Computation, 2006. CEC 2006. IEEE Congress on
  • Conference_Location
    Vancouver, BC
  • Print_ISBN
    0-7803-9487-9
  • Type

    conf

  • DOI
    10.1109/CEC.2006.1688382
  • Filename
    1688382