DocumentCode
2462000
Title
Automatic Generation of Low-Power Circuits for the Evaluation of Polynomials
Author
Tisserand, Arnaud
Author_Institution
LIRMM, Univ. Montpellier 2, Montpellier
fYear
2006
fDate
Oct. 29 2006-Nov. 1 2006
Firstpage
2053
Lastpage
2057
Abstract
This paper presents a method for the automatic generation of high-performance and low-power arithmetic operators based on polynomial approximations. It deals with the bit-level representation of the polynomial coefficients, the intermediate computations width, the approximation and the rounding errors. The generated operators are small, fast and numerically validated at design time. Some examples have been implemented on FPGAs.
Keywords
field programmable gate arrays; polynomial approximation; FPGA; bit-level representation; low-power arithmetic operators; low-power circuits; polynomial approximations; polynomial coefficients; polynomial evaluation; Application specific integrated circuits; Approximation error; Arithmetic; Field programmable gate arrays; Function approximation; Hardware; Parallel processing; Polynomials; Roundoff errors; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on
Conference_Location
Pacific Grove, CA
ISSN
1058-6393
Print_ISBN
1-4244-0784-2
Electronic_ISBN
1058-6393
Type
conf
DOI
10.1109/ACSSC.2006.355128
Filename
4176938
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