A Multi-Mode Low-Energy Binary Adder

Conventional binary adders have constant energy consumption at constant supply voltage. A large portion of the total energy is typically consumed by the parallel prefix tree, due to high output loads and long wires. This paper presents a multi-mode addition algorithm, which allows a partial shutdown of the prefix tree to achieve lower energy consumption at slower speeds. The algorithm applies to all sparse tree adders in general. The number of modes is equal to the number of sum-blocks in the adder. Implementation results at different supply voltages are reported.