DocumentCode :
2462309
Title :
Analysis and Reduction of Noise in Fractional PLL
Author :
Patel, Govind Singh ; Sharma, Sanjay
Author_Institution :
ECED, Lingayas Univ., Faridabad, India
fYear :
2012
fDate :
4-6 June 2012
Firstpage :
507
Lastpage :
511
Abstract :
The aim of this paper is analysis and presenting a technique to reduce phase noise in fractional frequency synthesizer for pure signal synthesis. To reduce phase noise of synthesizer, first, we present a mathematical and accurate model of noise in Phase Locked Loop(PLL) based fractional frequency synthesizer with take into account noise of its component. Then we predict output phase noise in term of its parameters. Finally, we describe as effective technique for noise in fractional frequency synthesizer by CppSim simulator. The Behavioral Simulation results show the performance of the fractional frequency synthesizer.
Keywords :
frequency synthesizers; phase locked loops; phase noise; CppSim simulator; behavioral simulation; fractional PLL; fractional frequency synthesizer; mathematical model; phase locked loop; phase noise reduction; signal synthesis; Detectors; Frequency synthesizers; Phase locked loops; Phase noise; Transfer functions; Voltage-controlled oscillators; Fractional Frequency Synthesis; Noise Reduction; PLL;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer, Consumer and Control (IS3C), 2012 International Symposium on
Conference_Location :
Taichung
Print_ISBN :
978-1-4673-0767-3
Type :
conf
DOI :
10.1109/IS3C.2012.134
Filename :
6228357
Link To Document :
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