Title :
On the growth mechanisms of GaAs nanowires by Ga-assisted chemical beam epitaxy
Author :
Garcia Nunez, C. ; Brana, A.F. ; Lopez, N. ; Garcia, B.J.
Author_Institution :
Dept. Fis. Apl., Grupo de Electron. y Semicond., Univ. Autonoma de Madrid (UAM), Madrid, Spain
Abstract :
GaAs nanowires (NWs) growth kinetics by Ga-assisted chemical beam epitaxy on Si(111) substrates is studied as a function of the initial Ga catalyst dimensions and growth parameters such as substrate temperature and V/III flux ratio. The preparation method for substrates is optimized in order to obtain a surface oxide with a thickness around 0.5 nm, allowing the decomposition of Ga metalorganic precursor and the preferential growth of GaAs NWs at the oxide pinholes. The successful self-formation of Ga droplets over the slightly oxidized Si surface has been observed by scanning electron microscopy (SEM), whose initial size is demonstrated to affect both the NW growth rate and the resultant NW aspect ratio. NW morphology is thoroughly analyzed by SEM, showing a self-organized array of vertically aligned match-shaped GaAs NWs with a hexagonal footprint. In addition, the crystalline structure of NWs is monitored in-situ by reflection high-energy diffraction (RHEED), showing pure zincblende phase along the whole NW stem.
Keywords :
III-V semiconductors; catalysis; chemical beam epitaxial growth; crystal structure; dissociation; drops; gallium arsenide; nanofabrication; nanowires; oxidation; reflection high energy electron diffraction; scanning electron microscopy; surface structure; Ga droplets; Ga metalorganic precursor; Ga-assisted chemical beam epitaxy; GaAs; RHEED; SEM; Si; Si(111) substrates; V-III flux ratio; aspect ratio; crystalline structure; decomposition; growth kinetics; growth mechanisms; hexagonal footprint; initial Ga catalyst dimensions; morphology; nanowire growth rate; nanowire stem; oxidation; oxide pinholes; preferential growth; reflection high-energy diffraction; scanning electron microscopy; self-formation; self-organized array; size 0.5 nm; substrate temperature; surface oxide; vertically aligned GaAs nanowires; zincblende phase; Electron devices; Gold; Nanoscale devices; Silicon; Substrates; Surface morphology; CBE; GaAs; RHEED; nanowires;
Conference_Titel :
Electron Devices (CDE), 2015 10th Spanish Conference on
Conference_Location :
Madrid
DOI :
10.1109/CDE.2015.7087447