Title :
Reduced-routing complexity decoder for high-rate QC-LDPC codes
Author :
Niu, Yong ; Xiao, Zhenyu ; Jin, Depeng ; Su, Li ; Zeng, Lieguang
Author_Institution :
Dept. of Electron. Eng., Tsinghua Univ., Beijing, China
Abstract :
This paper presents a high-throughput and routing complexity reduced decoder for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes in the high rate wireless personal area network applications (WPAN). Our selected code is the rate-1/2 QC-LDPC code in IEEE P802.11ad/D1.0. A new decoder architecture is proposed. The message paths between variable nodes and check nodes are constructed by a fixed wire network. Compared to the fully parallel architecture, routing complexity of the new architecture is reduced greatly. The decoder is implemented using FPGA, and a data rate of 1.21 Gbps can be achieved in the air.
Keywords :
cyclic codes; field programmable gate arrays; parity check codes; personal area networks; telecommunication network routing; telecommunication standards; wireless LAN; FPGA; IEEE P802.11ad; QC-LDPC codes; check nodes; field programmable gate arrays; fixed wire network; message paths; quasi-cyclic low-density parity check codes; reduced-routing complexity decoder; variable nodes; wireless personal area network; Complexity theory; Decoding; Iterative decoding; Random access memory; Wireless personal area networks; Wires; LDPC decoder; QC-LDPC; WPAN;
Conference_Titel :
Computational Problem-Solving (ICCP), 2011 International Conference on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4577-0602-8
Electronic_ISBN :
978-1-4577-0601-1
DOI :
10.1109/ICCPS.2011.6089946
